1. Field of the Invention
The present invention relates to a solid state image capture device, an analog/digital conversion method for the solid state image capture device, and an image capture device.
2. Description of Related Art
As one scheme for a solid state image capture device, techniques called column AD conversion scheme are known. According to the techniques of the column AD conversion scheme, in an amplification type solid state image capture device which is a type of a X-Y address type solid state image capture device, e.g., an MOS (including CMOS) type solid state image capture device, an analog/digital (AD) converter is disposed, for example, per each pixel column, i.e., column parallel, with respect to a pixel array unit having pixels each including a photoelectric conversion element disposed two-dimensionally in a matrix shape, and an analog pixel signal read from each pixel of the pixel array unit is converted into digital data and outputted.
In AD converters disposed column parallel, a comparator compares each analog pixel signal read from each pixel of the pixel array unit on the row unit basis via a column signal line with a reference signal of a ramp waveform to generate a pulse signal corresponding to each magnitude of reference components and signal components and having a magnitude (pulse width) in a time axis direction. A counter unit counts a predetermined clock during a period of the pulse width of the pulse signal, and the count value of the counter unit is converted into digital data corresponding to the amplitude of the pixel signal to thus perform an AD conversion operation.
In order to realize high speed AD conversion in a solid state image capture device of the column AD conversion scheme, a clock conversion unit for generating a clock faster than a master clock is provided, and a high speed clock generated by the clock conversion unit is used as a count clock of the counter unit, whereby a processing speed of an AD conversion process is not limited by the speed (frequency) of the master clock (e.g., refer to Japanese Unexamined Patent Application Publication No. 2005-303648, Patent Document 1).
More specifically, the counter unit counts the pulse width of the pulse signal until a comparison end of the comparator at high speed clock, and holds the count value at the comparison completion time. While at a first count process, down count is performed for the reference components (reset components) read from a pixel, at a second count process, up count is performed for the signal components read from the pixel.
By performing the count process twice, the count value held after the second count process becomes a difference between the count values of the first count process. In other words, two count processes in which the count mode is changed are executed when the count process is executed based on high speed clocks, and whereby a digital value corresponding to a difference between the reference components and signal components can be obtained as the count value of the second count process.